HW-V5-ML561-UNI-G【PDF 57/140 页】EVALUATION PLATFORM VIRTEX-5

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Test Setup

strobe, a random value can be applied to data bits from one cycle to another. A 63-bit

PRBS6 (1) (PRBS of order 6) test pattern stimulus is used for this analysis. The value of

this PRBS6 string is 63’h03F5_66ED_2717_9461 , that is:

63’b000001111110101011001101110110100100111000101111001010001100001 .

The HyperLynx stimulus setup is for: a 2-sequence repeat, 10 bits skipped, 1 eye, and

0% jitter.

Test criteria

Quality of a signal is measured in terms of the opening of the signal eye at the receiver

input for both the amplitude and the width. DDR2 SDRAM (Component and DIMM)

interfaces utilize the SSTL_18 I/O standard, and the QDRII SRAM interface utilizes

the HSTL 1.8V I/O standard. For each of these two I/O standards, the eye mask is

defined by the trapezoid enclosed by the following four voltage thresholds at the

receiver input:

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VIH(ac)-min at the rising edge

VIH(dc)-min at the falling edge

VIL(dc)-max at the rising edge

VIL(ac)-max at the falling edge

Refer to Figure 7-1 for the definition of voltage levels with regard to the trapezoidal

eye mask. Refer to “Terminology,” page 9 for definitions of the voltage thresholds.

Because the HyperLynx SI simulation software does not support a trapezoidal mask

definition, two separate triangular masks for VIH and VIL are defined, as shown in

Figure 7-2 , such that the third vertex of triangle falls on the VREF axis.

VDDQ

VOH(dc)

VIH(dc)

VIL(dc)

VREF

VIH(ac)

VIL(ac)

VOH(ac)

VOL(ac)

VOL(dc)

VSS

UG199_c7_01_062707

Figure 7-1:

Single Trapezoid Eye Mask Definition

1. A maximal-length PRBS test sequence of order n generates all (2 n – 1), n-bit combinations of test sequences

(except all 0s). Thus the test sequence contains one n-bit long consecutive string of 1s and two (n-1)-bit long

consecutive strings of 0s. With the PRBS6 test pattern, at the highest test frequency of 333 MHz (that is, the bit

time is 1.5 ns), measurements in this setup result in a maximum settling time of (1.5 ns * 5) = 7.5 ns for a logic

Low, and a maximum settling time of (1.5 ns * 6) = 9 ns for a logic High. 7.5 ns is sufficient time for the test

signal to reach a steady state before the next transition. Thus a PRBS test pattern of higher order, such as 7 or

9, does not change the eye pattern, as proven by sample simulation of one test signal with PRBS6, PRBS7, and

PRBS9 stimuli.

Virtex-5 FPGA ML561 User Guide

UG199 (v1.2.1) June 15, 2009

57

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